As integrated circuits (ICs) have become increasingly miniaturized and complex, manufacturing challenges have arisen. Such challenges for example include barriers to interconnect scaling. 3D integrated circuits have been proposed as one solution to overcome such challenges. By utilizing fast and densely packed inter-die vias, 3D ICs can provide the possibility for continued high performance using CMOS technology, for example.
Developing 3D ICs, however, presents its own set of unique challenges. Among other things, a critical feature of any semiconductor device fabrication process is testing. In conventional integrated circuit manufacturing processes, for example, after a wafer is processed, the wafers are probed using an external probing device. Through this process, individual dies on the wafers are tested for functionality before the dies are separated and individually packaged. This process is often referred to as “wafer sort”. Testing may also be performed at a “final test” (FT) phase to insure that a final packaged IC functions properly. Final test in the context of 3D integrated circuit manufacture generally refers to a final product test that occurs after 3D assembly of the different die layers into one device or product.
As IC devices have become smaller, testing has also become more complex and challenging. Increasingly, it has become necessary to design an IC chip for testing ahead of time. Testing techniques and design for testing (DFT) solutions are fairly well established in the context of 2D devices, but have not yet been developed as robustly in the context of 3D devices. 3D integrated circuits present some unique challenges to testing. These testing challenges can relate, among other things, to more difficult probe access to wafers, difficulty of test access to modules in stacked wafers and dies, thermal concerns, challenges to testability of certain designs, cost of testing solutions, and new defects that can potentially arise from processing steps unique to 3D ICs such as wafer thinning, alignment and bonding. The processing steps unique to 3D integrated circuit can necessitate additional testing processes: for example, a first step to insure that a device is working properly on each of its 2D levels (for example, a pre-bond wafer/die test), and a second step (for example, a post-bond wafer/die test) to insure that the device is properly functioning in terms of its vertical connections.
Testing solutions have sometimes not kept pace with advances in architectures, design automation tools, and yield enhancement techniques. Cost of testing and the consequences of design decisions on testing can often be unanticipated handicaps to developing efficient processes for manufacturing 3D integrated circuits.
Various embodiments of the present disclosure seek to improve upon testing techniques and Design For Testing (DFT) solutions for testing 3D ICs, as well as 2D ICs.